High efficiency switching CMOS power amplifiers for wireless communications

High-efficiency performance is one of the most important requirements of power amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS PAs for watt-level applications is a challenging task. This dissertation focuses on the development of the design method for highly efficient CMOS PAs to overcome the fundamental difficulties presented by CMOS technology. In this dissertation, the design method and analysis for a high-power and highefficiency class-E CMOS PA with a fully integrated transformer have been presented. This work is the first effort to set up a comprehensive design methodology for a fully integrated class-E CMOS PA including effects of an integrated transformer, which is very crucial for watt-level power applications. In addition, to improve efficiency of cascode class-E CMOS PAs, a charging acceleration technique is developed. The method accelerates a charging speed to turn off the common-gate device in the off-state, thus reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an improvement of approximately 6% in the power added efficiency. The proposed cascode class-E PA structure is suitable for the design of high-efficiency class-E PAs while it reduces the voltage stress across the device.Ph.D.Committee Chair: Joy Laskar; Committee Member: Emmanouil M. Tentzeris; Committee Member: Gordon L. Stuber; Committee Member: John D. Cressler; Committee Member: Paul A. Koh

A Dual-Mode InGaP/GaAs HBT Power Amplifier Using a Low-Loss Parallel Power-Combining Transformer with IMD3 Cancellation Method

A dual mode InGaP/GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) using a parallel power-combining transformer (PCT) is presented herein. A low loss transformer is implemented on a printed circuit board (PCB) to improve the passive efficiency of a PCT. Dual-mode operation is applied to reduce the current consumption at a low power level. In the low-power (LP) mode, one of the individual amplifiers is turned off to reduce the current consumption. Additionally, a third-order intermodulation distortion (IMD3) cancellation method using a PCT combiner is proposed to improve linearity performance. Nonlinear IMD3 components from each amplifier cancel each other out through magnetic coupling in the secondary winding of the PCT. The implemented PA achieves a saturated output power of 33.8 dBm and a peak power-added efficiency (PAE) of 54.5% at 0.91 GHz with a 5-V power supply. An average output power of 25.2 dBm with an adjacent channel leakage ratio (ACLR) of −42 dBc is delivered when the PA is tested with an orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulated (64-QAM) signal with a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB. When compared with the high-power (HP) mode operation, the LP mode operation could save 48% of the current consumption at an average output power of 10.4 dBm

An Amplitude and Phase Mismatches Calibration Technique for the LINC Transmitter With Unbalanced Phase Control

The linear amplifier with nonlinear components (LINC) is highly efficient because it uses a highly efficient nonlinear power amplifier (PA). However, the linearity performance of the LINC system is easily degraded by amplitude and phase mismatches between the two paths. In this paper, we propose a novel mismatch calibration technique for the LINC system that calibrates both phase and amplitude mismatches with only phase control. The technique detects mismatches between two paths without any iteration using predefined five test vector signals. In addition, this technique corrects the path mismatches using unbalanced phase control. Therefore, the proposed scheme does not require additional amplitude mismatch control blocks such as dc/dc converters or low drop output regulators (LDO). The linearity performance of the proposed LINC system is measured with 7-MHz bandwidth orthogonal frequency-division multiplexing (OFDM) signals. According to the measurement results, the proposed technique significantly enhances linearity. The measurement results also shows that the proposed LINC system satisfies the error vector magnitude (EVM) requirement for a 16-state quadratic amplitude modulation (QAM) signal (-24 dB) and a 64-QAM signal (-31 dB) up to 3.8- and 2.35-dB amplitude mismatches, respectively, with any phase mismatch.close4

An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current

An external capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were -60 and -35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of 19 mu V/mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was 275 mu A, the LGS consumed only 7 mu A. The area was 0.008 mm(2) with 4-pF on-chip capacitance for compensation

Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers

A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It is based on the analysis of the operation and power loss mechanism of class-E PAs, which includes the effects of a finite dc-feed inductance and an impedance matching transformer. Using the proposed approach, a class-E PA with a 2 x 1:2 step-up on-chip transformer was implemented in a 0.18-mu m CMOS technology. With a 3.3 V supply, the fully integrated PA achieves an output power of 2 W and a power-added efficiency of 31% at 1.8 GHz.ope

A Fully Integrated Dual-Mode CMOS Power Amplifier With an Autotransformer-Based Parallel Combining Transformer

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.7 and 15.7 dBm average output powers with PAEs of 17.1% and 13%, in HP and LP modes, respectively, while satisfying a -25 dB error vector magnitude and spectral mask requirements. Operating the PA in the LP mode can save more than 40% of the current consumption at a 10-dBm average output power when compared with that in the HP mode

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mu m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 801.16e signals.ope

A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter with a Nonisolated Power Combiner

This brief presents a nonisolated multilevel linear amplifier with nonlinear component (LINC) power amplifier (PA) implemented in a standard 0.18-??m complementary metal-oxide-semiconductor process. Using a nonisolated power combiner, the overall power efficiency is increased by reducing the wasted power at the combined out-phased signal; however, the efficiency at low power still needs to be improved. To further improve the efficiency of the low-power (LP) mode, we propose a multiple-outputpower-level LINC PA, with load modulation implemented by switches. In addition, analysis of the proposed design on the system level as well as the circuit level was performed to optimize its performance. The measurement results demonstrate that the proposed technique maintains more than 45% power-added efficiency (PAE) for peak power at 21 dB for the high-power mode and 17 dBm for the LP mode at 600 MHz. The PAE for a 6-dB peak-to-average ratio orthogonal frequency-division multiplexing modulated signal is higher than 24% PAE in both power modes. To the authors' knowledge, the proposed output-phasing PA is the first implemented multilevel LINC PA that uses quarter-wave lines without multiple power supply sources.clos

A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz